#ifndef HAL_UART_CONFIG_H_
#define HAL_UART_CONFIG_H_

#define UART0_ENABLE							TRUE

#define UART0_DATA_LENGTH						UART_8_BITS_DATA_LENGTH

#define UART0_ENABLE_PARITY_CHECKING			FALSE

#define UART0_PARITY							ODD_PARITY

#define UART0_STOP_BIT							STOP_BIT_1

#define UART0_FRACTIONAL_BAUDRATE_DIVISOR		5

#define UART0_FRACTIONAL_BAUDRATE_MULTIPLIER	14

#define UART0_BAUDRATE_DIVISOR					12

#define UART0_ENABLE_INTERRUPT					TRUE

#define UART0_INTERRUPT_PRIORITY				15

#define UART0_ENABLE_DATA_TRANSMITTED_INTERRUPT			TRUE

#define UART0_ENABLE_DATA_RECEIVED_INTERRUPT			TRUE

#define UART0_ENABLE_RECEIVING_DATA_ERROR_INTERRUPT		FALSE




#define UART2_ENABLE							FALSE

#define UART2_DATA_LENGTH						UART_8_BITS_DATA_LENGTH

#define UART2_ENABLE_PARITY_CHECKING			FALSE

#define UART2_PARITY							ODD_PARITY

#define UART2_STOP_BIT							STOP_BIT_1

#define UART2_FRACTIONAL_BAUDRATE_DIVISOR		5

#define UART2_FRACTIONAL_BAUDRATE_MULTIPLIER	14

#define UART2_BAUDRATE_DIVISOR					12

#define UART2_ENABLE_INTERRUPT					FALSE

#define UART2_INTERRUPT_PRIORITY				15

#define UART2_ENABLE_DATA_TRANSMITTED_INTERRUPT			FALSE

#define UART2_ENABLE_DATA_RECEIVED_INTERRUPT			FALSE

#define UART2_ENABLE_RECEIVING_DATA_ERROR_INTERRUPT		FALSE




#define UART3_ENABLE							FALSE

#define UART3_DATA_LENGTH						UART_8_BITS_DATA_LENGTH

#define UART3_ENABLE_PARITY_CHECKING			FALSE

#define UART3_PARITY							ODD_PARITY

#define UART3_STOP_BIT							STOP_BIT_1

#define UART3_FRACTIONAL_BAUDRATE_DIVISOR		5

#define UART3_FRACTIONAL_BAUDRATE_MULTIPLIER	14

#define UART3_BAUDRATE_DIVISOR					12

#define UART3_ENABLE_INTERRUPT					FALSE

#define UART3_INTERRUPT_PRIORITY				15

#define UART3_ENABLE_DATA_TRANSMITTED_INTERRUPT			FALSE

#define UART3_ENABLE_DATA_RECEIVED_INTERRUPT			FALSE

#define UART3_ENABLE_RECEIVING_DATA_ERROR_INTERRUPT		FALSE

#endif /*HAL_UART_CONFIG_H_*/
